The present invention relates to a method of manufacturing a semiconductor device wherein a dense array of conductive lines is etched at a rate faster than the rate at which the conductive lines are etched in a bordering open field.
The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. This objective becomes particularly difficult to achieve given the economic pressure for high speed production and challenges the limitations of semiconductor technology. Thus, the combined requirements of high speed and high density conductive wiring patterns pose a challenge which, to date, has not been satisfactorily achieved.
A traditional method for forming a dense array of conductive lines comprises the use of a subtractive etch back step as the primary metal-patterning technique. This traditional technique basically comprises forming an insulating dielectric layer on a substrate, such as monocrystalline silicon, depositing a conductive layer, such as aluminum, tungsten, polysilicon, tungsten silicide (WSi), or titanium silicide, forming a photo-resist mask having a pattern defining a dense array of conductive lines bordered by an open field wherein the distance between the conductive lines is considerably greater than the distance between conductive lines in the dense array, and etching through the mask. Typically, the etch rate in the dense array of conductive lines is slower than the corresponding open field.
Etching is normally conducted until a material is substantially removed between the conductive lines of the dense array along with any residues which may have formed. Conventionally, overetching must be performed to remove a portion of the underlying oxide to ensure complete removal of products between conductive lines to avoid shorting. As employed throughout this application, the expression xe2x80x9copen fieldxe2x80x9d denotes an area wherein conductive lines are separated by a distance of at least 2.0 microns, while the expression xe2x80x9cdense arrayxe2x80x9d denotes a pattern of conductive lines which are separated by a distance of less than 1.0 micron.
A problem typically encountered when etching a layer to form a dense array of lines bordered by an open field is that the etch rate of materials within the dense array is inevitably slower than the etch rate of materials in the bordering open field. This etch rate differential is commonly referred to as the xe2x80x9cetch rate microloadingxe2x80x9d and results in xe2x80x9cundercuttingxe2x80x9d of the material within the dense array of lines.
The etch rate differential between the rate within the dense array as compared with the bordering open field, or etch rate microloading, generates numerous problems which are exacerbated as integration increases and smaller interwiring spacings are required within dense arrays. For example, the etch rate microloading phenomenon causes problems such as undercutting of the various layers within the dense array, since it is virtually impossible to determine the etch end point within the dense array with a reasonable degree of accuracy. Significantly, the speed at which semiconductor devices can be manufactured is compromised because more time is required to adequately etch layers within the dense array. Additional problems stemming from the etch rate microloading include the formation of sloping profiles on leading and tailing conductive lines, and increased time and work for planarizing a subsequently applied dielectric layer.
U.S. Pat. No. 5,702,564, issued on Dec. 30, 1997 a method is disclosed for reducing undercutting of conductive lines within a dense array by changing one or more of the initial etching conditions at a strategic point in the etching process.
Copending application Ser. No. 08/423,495, filed on Apr. 19, 1995, now abandoned, discloses a method or preventing undercutting of conductive lines in a dense array by providing one or more non-functional dummy or conductive lines in the bordering open field.
Copending application Ser. No. 08/657,261 (Our Docket No. 1033-154), discloses a method of increasing the etch rate within the dense array by etching the conductive layer through a mask with a high density plasma generated by a gas flow containing a sufficient amount of nitrogen.
Heightened demands for minimal interwiring spacings associated with ultra large scale integration amplify the impact of the etch rate microloading phenomenon on the manufacturing of semiconductor devices. For example, upon detection of the etch end point of a metal layer in an open field bordering a dense array, a substantial amount of metal remains between conductive lines within the dense array. It was found that the etch rate differential becomes even more pronounced as the distance between the conductive lines of the dense array decreases. Thus, as integration increases, a much longer overetch time is required to ensure that metal lines within the dense array are formed free of bridging. Longer overetch time necessarily involves longer processing time and, hence, reduced throughput. Moreover, a longer overetch time increases the amount of resist lost and requires a deeper oxide cut in the open field. These adverse consequences of the etch rate microloading phenomenon render it extremely difficult to continue employing conventional methodology for submicron geometry etching of conductive lines within a dense array.
There exists a need to provide semiconductor methodology, wherein the etch rate microloading is reduced to zero and even reversed by an efficient, cost-effective and simplified technique to satisfy the demands of ultra large scale integration for increasingly denser arrays with minimal interwiring spacing between conductive lines.
An advantage of the present invention is a method of manufacturing a semiconductor device having a dense array of conductive lines wherein the etch rate within the dense array is increased to greater than the etch rate in the bordering open field.
Additional advantages of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device having a dense array of conductive lines comprising: forming an insulating layer; forming a layer of conductive material on the insulating layer; forming a polysilicon capping layer on the conductive layer; forming a mask on the polysilicon capping layer, which mask contains a pattern defining a dense array of conductive lines bordered by an open field; and etching the polysilicon capping layer through the mask with a high density plasma generated in a plasma processing chamber while selectively controlling a source power and a bottom power to increase the etch rate of the polysilicon capping material within the dense array to greater than the etch rate of the polysilicon capping material in the open field.
U.S. Pat. No. 5,795,829, issued on Aug. 18, 1998, discloses a method of increasing the etch rate within the dense array by etching the conductive layer through a mask with a high density plasma generated by a gas flow containing a sufficient amount of nitrogen.